TSMC's Pricing Power: How One Foundry Sets the Cost of Every Advanced Chip

TSMC is the world's largest foundry by revenue, and at the leading edge it is where the big designers line up: DigiTimes reported in August 2025 that Apple, Qualcomm, AMD, MediaTek, Broadcom and Intel were set to take shares of its 2nm production, with Apple slated for nearly half. That pricing power runs through a single lever: how it prices wafers. TSMC does not sell transistors or finished chips. It sells a wafer at a per-node price, and it reports its own sales as wafer revenue split by node. When the cost of a leading-edge wafer rises at its fabs in Taiwan and, increasingly, Arizona, the increase does not stay in Hsinchu. It cascades down through chip designers, device makers, and eventually the price on the shelf.

How much does a TSMC wafer cost?#

Start with the unit of sale. TSMC prices by process node. A wafer of N5, its 5nm-class process, costs a certain amount; N3 more; N2 more again. The node names are labels, not rulers: as IEEE Spectrum put it, a node name no longer reflects the size of any particular chip feature. In the standard arrangement the customer buys the wafer, not the working dies on it. That detail matters more than it looks, because the yield risk sits with the fabless customer. If half the chips on a wafer are defective, that is mostly the designer's loss. TSMC does not comment on its pricing, so the terms any one large customer negotiates are private.

Because TSMC does not publish node pricing, every figure comes from press reports citing industry sources. DigiTimes reported in November 2022 that wafer prices for 3nm topped 20,000 dollars. In June 2025, TrendForce relayed a Commercial Times report that 2nm wafers had reached about 30,000 dollars, and in September 2025 it relayed China Times reporting that N3P wafers cost 20% more than N3E. The 3nm figure dates from 2022, so its gap to the 2025 2nm figure is a rough guide, not a measured step; China Times, relayed by TrendForce, reported that 2nm prices are at least 50% higher than 3nm. The direction is not in doubt. In its September 2026 foundry ranking, TrendForce said strong demand for AI server chips kept TSMC's 5/4nm and 3nm capacity fully booked. Reuters, citing Nikkei Asia, reported in July 2026 that TSMC will raise prices by up to 10% from 2027. TSMC did not confirm, and a spokesperson said: "Our pricing strategy is strategic, not opportunistic."

Underneath all of this is an economic shift. For decades, each new node was also cheaper per transistor. That was the economic engine of Moore's Law: you paid more per wafer but got so many more transistors that each one cost less. Google's Milind Shah has argued that this stopped long ago. As PC Gamer reported in February 2024, his figures put the cost of 100 million transistor gates at about the same level as the 28nm generation, with 5nm and 3nm slightly pricier per transistor. PC Gamer's writer called the claim incomplete, since consumer CPUs have not risen in price the same way, but the direction explains why TSMC's wafer price now shows up in the final product instead of being absorbed by density gains.

Why mask and design costs keep designers at TSMC#

The grip does not come from the wafer price alone. It comes from how hard it is to leave. A chip is co-designed against a specific foundry's process design kit, its design rules, and its IP libraries. Move a finished design to another foundry and you do not copy a file. You redo the physical implementation, re-license and re-qualify IP blocks, cut a new set of photomasks, and re-validate the whole thing. TSMC does not publish what it charges for a mask set. What is published is the bigger number around it: the research firm International Business Strategies (IBS) estimates that designing a 5nm chip costs 416 million dollars on average and a 3nm chip up to 590 million dollars, as cited in Silvaco's 2024 SEC filing. Masks themselves are changing too. In September 2026, TSMC and ASML announced an initiative to move from today's 6-inch photomasks to 12-inch ones, with a pilot line targeted by 2031, which they say should raise fab productivity and reduce chipmaking costs.

That sunk cost is the moat. NVIDIA says its Blackwell GPUs are made on a custom TSMC 4NP process, and DigiTimes reported that Apple, Qualcomm, AMD and MediaTek were among the companies lining up for TSMC's 2nm. Even Intel, which runs its own fabs and sells foundry services against TSMC, had TSMC make its Lunar Lake laptop chips on N3B and N6, eeNews Europe reported in June 2024. The dependency is not sentimental. It is structural.

Why big AI chips feel wafer prices most#

How a wafer price increase reaches a final price depends almost entirely on die size and yield, which is why a flat dollars-per-wafer figure is misleading. What matters is the cost per good die. A 300mm wafer has about 70,700 square millimeters of area. By the standard dies-per-wafer formula, it fits about 640 candidate dies of 100 square millimeters, but only about 63 of 814 square millimeters, the size NVIDIA gives for its H100 GPU die. TSMC's CoWoS page describes an interposer of twice the reticle size as about 1,700 square millimeters, which puts one reticle, the largest area a scanner prints in one exposure, near 850. A die like H100 is close to that ceiling.

Those figures are our own arithmetic. The 3,000-dollar rise is 10% of the 30,000-dollar 2nm price reported in 2025, and the die counts ignore edge exclusion and the gaps between dies, so real counts are a little lower. They show why TSMC's pricing bites hardest on AI accelerators and high-end GPUs rather than phones. Big dies have nowhere to hide the cost. From there the increase compounds through packaging, the board, the device maker's margin, and retail markup before it ever reaches a consumer.

Why Samsung SF2 and Intel 18A have not cut TSMC's prices#

There are alternatives, and both now ship. Samsung's SF2, its first 2nm-class process, went into mass production in the fourth quarter of 2025 with the Exynos 2600, SamMobile reported. Intel 18A is the process behind its Core Ultra series 3 (Panther Lake) chips, which Intel said were in production in October 2025. On its July 2026 earnings call, Intel said 18A yields were trending ahead of the targets it set in March, and that it had committed to a high-volume ramp of its next node, 14A, in 2028, after risk production in the second half of 2027. But the leading edge is won on three things, and they are precisely TSMC's strengths.

The scale gap is wide. TrendForce's ranking for the second quarter of 2026 gave TSMC a 72.5% foundry market share and Samsung, in second place, 5.9%. TSMC reported 40.20 billion dollars of revenue for that quarter, while Intel said its external foundry revenue was 293 million dollars. Samsung's 2nm yields were reported at just over 50% in January 2026. Until a rival matches TSMC's yield, ecosystem, and packaging at scale, the alternatives discipline pricing only at the margin. They do not break the lock.

Does building in Arizona make TSMC chips cheaper?#

Policy has tried to change the map. In November 2024 the Biden administration finalized a 6.6 billion dollar CHIPS and Science Act award for TSMC's Arizona fabs, along with 5 billion dollars in loans, Manufacturing Dive reported. TSMC's planned Arizona investment has grown since: 165 billion dollars in March 2025, then another 100 billion dollars announced in July 2026, for a total TSMC now gives as 265 billion dollars, covering fabs, advanced packaging, and research. Its first Arizona fab began high-volume production on N4 in the fourth quarter of 2024. The second is targeting N3 volume production in the second half of 2027, the third is slated for N2 and A16 with volume production targeted by the end of the decade, and construction of a fourth began in early 2026. Subsidies offset some of the capital cost.

But subsidies do not repeal geography. TSMC chairman C.C. Wei said in July 2026 that ramping overseas fabs would dilute gross margin by 2 to 3 percentage points at first, widening to 3 to 4 points as they scale, TrendForce reported. Reuters' account of the Nikkei Asia report on 2027 price rises said they are meant to offset higher costs for materials, equipment, and overseas plant construction. The Arizona buildout is about resilience and geopolitics, spreading a highly concentrated supply chain beyond a single island, not about making advanced chips cheaper.

Who absorbs TSMC's price increases#

The squeeze is not evenly distributed. Volume and long relationships are worth something: DigiTimes reported in August 2025 that Apple alone was set to take nearly half of TSMC's 2nm production, with Qualcomm second. Scale buys a place at the front of the line.

Everyone smaller pays closer to full freight: the same wafer, masks, and design cost, with less volume to spread them over. That gives smaller designers a reason to stay on older, cheaper, still-capable nodes such as N6, N7, or N16, or to wait a generation. Older nodes are still a real business for TSMC: in the third quarter of 2026, nodes older than 7nm made up 21% of its wafer revenue. They are not a refuge from price rises either, since the Nikkei Asia report said 12nm, 16nm, and 28nm prices would also rise by up to 10%.

TSMC's power is narrower and more durable than the label biggest chipmaker suggests. It sits at the leading edge, and it rests on yield, ecosystem, and packaging at a scale that left Samsung, in second place, with 5.9% of the foundry market to TSMC's 72.5% in TrendForce's ranking. That scale shows in the 66.4% gross margin TSMC reported for the third quarter of 2026. Every frontier phone chip, GPU, and AI accelerator made there carries a TSMC toll, and as cost per transistor stops falling, that toll increasingly shows up in prices instead of being absorbed by density gains. The open question for the next few years is not whether Samsung, Intel, or Arizona exist. It is whether any of them produces real pricing competition, or just a more geographically spread version of the same dependency.