TSMC's Pricing Power: How One Foundry Sets the Cost of Every Advanced Chip

TSMC is not just the world's largest chip manufacturer. At the leading edge it is the only one that reliably works at volume, which makes it something closer to a toll booth on every advanced semiconductor. That power runs through a single lever: how it prices wafers. TSMC does not sell transistors or finished chips. It sells a wafer at a per-node price, and it books that price whether the good chips on the wafer come out or not. When the cost of a leading-edge wafer rises at its fabs in Taiwan and, increasingly, Arizona, the increase does not stay in Hsinchu. It cascades down through chip designers, device makers, and eventually the price on the shelf.

Wafers, not chips: how TSMC actually charges#

Start with the unit of sale. TSMC prices by process node. A wafer of N5, its 5nm-class process, costs a certain amount; N3 more; N2 more again. The customer buys the wafer, not the working dies on it. That detail matters more than it looks, because the yield risk sits with the fabless customer, not the foundry. If half the chips on a wafer are defective, that is the designer's loss, and they have already paid full freight for the silicon.

Two things are worth being precise about. First, the nanometer labels are marketing, not literal measurements. Nothing on an N3 chip is three nanometers wide. What actually changes from node to node is transistor density, the number of mask layers, and how much extreme ultraviolet lithography, or EUV, the process needs. Second, that is exactly why cost climbs. Each new node adds EUV layers and process steps, and the tools are staggering: a single EUV scanner from ASML costs well over one hundred million dollars, and the newer High-NA machines cost substantially more. TSMC does not publish node pricing, but customers and analysts broadly peg an N3 wafer somewhere around 18,000 to 20,000 dollars and N2 around 30,000, a jump on the order of 40 to 50 percent rather than the modest step it is sometimes framed as. Treat those as industry estimates, not official numbers.

Here is the part most coverage misses. For decades, each new node was also cheaper per transistor. That was the economic engine of Moore's Law: you paid more per wafer but got so many more transistors that each one cost less. At the leading edge, that has largely stalled. Density still rises, but wafer cost now rises about as fast, so by most industry analyses cost per transistor is roughly flat from the 5nm generation onward, and in some cases rising. The era of the automatically cheaper transistor is ending, and TSMC's pricing is where you see it first.

The iron grip: why leaving is nearly impossible#

The grip does not come from the wafer price alone. It comes from how hard it is to leave. A chip is not designed in the abstract. It is co-designed against a specific foundry's process design kit, its design rules, and its IP libraries. Move a finished design to another foundry and you do not copy a file. You redo the physical implementation, re-license and re-qualify IP blocks, cut new photomask sets, and re-validate the whole thing. For a leading-edge part, the masks, design, and verification effort alone runs into the hundreds of millions of dollars, and a port typically costs a year or more of engineering.

That sunk cost is the moat. Apple, Nvidia, AMD, and Qualcomm all have their most important products deeply committed to TSMC's process. Even Intel, which runs its own fabs and competes with TSMC as a foundry, has bought TSMC capacity for parts of some of its own products, which shows how universal the pull is. The dependency is not sentimental. It is structural.

How a wafer price reaches a price tag#

How a wafer price increase reaches a final price depends almost entirely on die size and yield, which is why a flat dollars-per-wafer figure is misleading. A wafer holds hundreds of dies, so what matters is the cost per good die, and that varies enormously with the size of the chip.

That is the real reason TSMC's pricing bites hardest on AI accelerators and high-end GPUs rather than phones. Big dies have nowhere to hide the cost. From there the increase compounds through packaging, the board, the device maker's margin, and retail markup before it ever reaches a consumer.

Why the competition does not discipline the price yet#

There are alternatives. Samsung's SF2, its 2nm-class process, is in mass production, and Intel is pushing its 18A node, now shipping, and its next node, 14A. Neither is vaporware, and both keep improving. But the leading edge is won on three things, and they are precisely TSMC's strengths.

Samsung has repeatedly fought yield problems on its most advanced nodes. Intel Foundry is still proving it can win outside customers at volume rather than filling its own lines. And TSMC holds something like 90 percent of the world's most advanced capacity, by industry estimates. Until a competitor matches its yield, ecosystem, and packaging at scale, the alternatives discipline pricing only at the margin. They do not break the lock.

Geography, subsidies, and the Arizona premium#

Policy has tried to change the map. Under the US CHIPS and Science Act, TSMC has been building in Arizona. In March 2025 it said it would raise its total planned US investment to 165 billion dollars, adding 100 billion dollars on top of an existing 65 billion, for three new fabs, two advanced packaging plants, and a research center. Its first Arizona fab began volume production of 4nm-class chips in late 2024, and 2nm production is planned. Subsidies offset some of the capital cost.

But subsidies do not repeal geography. A US fab costs more to run than a Taiwanese one, and that gap tends to surface in wafer prices rather than disappear. The Arizona buildout is fundamentally about resilience and geopolitics, spreading the world's most concentrated supply chain beyond a single island, not about making advanced chips cheaper. The systemic exposure, most of the planet's leading-edge output sitting in Taiwan, is being reduced slowly and at a premium.

Who actually absorbs the increase#

The squeeze is not evenly distributed. The largest buyers get priority allocation and better terms, because volume and long relationships are worth something. By multiple reports, Apple secured more than half of TSMC's initial N2 capacity for its next-generation chips. Scale buys a place at the front of the line.

Everyone smaller pays closer to full freight: wafer, masks, and design cost, with no volume discount to soften it. The practical result is that many smaller fabless companies and startups simply stay on older, cheaper, still-excellent nodes like N6, N7, or N16, or wait a generation, because the frontier is priced out of reach. Leading-edge silicon keeps consolidating among the handful of players who can afford the toll.

TSMC's power is narrower and more durable than the label biggest chipmaker suggests. It sits specifically at the leading edge, and it rests on being the only foundry that delivers the newest node at volume with good yield, backed by the ecosystem and packaging to match. Every frontier phone chip, GPU, and AI accelerator carries a TSMC toll, and as cost per transistor stops falling, that toll increasingly shows up in prices instead of being absorbed by density gains. The open question for the next few years is not whether Samsung, Intel, or Arizona exist. It is whether any of them produces real pricing competition, or just a more geographically spread version of the same dependency.