For twenty years the chip moat was the transistor. Since 2018 it has moved to the package: whoever runs the CoWoS, SoIC, and Foveros line decides whether an AI accelerator ships at volume. An interactive research edition.
A deep read — the full picture, with the receipts.
A modern AI accelerator is not one die. It is a stack of logic, high-bandwidth memory, and an interposer, bonded together. The hard part moved from etching the transistor to assembling that package at volume. That single shift explains why one phrase, CoWoS, now gates GPU supply.
The bottleneck moved off the transistor#
CoWoS, chip-on-wafer-on-substrate, became the phrase that gates GPU supply because a design can tape out cleanly and still not ship. The interposer-and-HBM assembly line is the real constraint. OSATs like ASE and Amkor serve a genuine market, but they cannot replicate CoWoS-class interposer integration or SoIC-class hybrid bonding at leading-edge volume.
Packaging is the binding constraint. Volume, not tape-out, decides who ships.
Desk: Advanced Packaging
Foundry and packaging landscape
- TSMCLeader
- SamsungSF2 2nm, chasing
- Intel18A / 14A, chasing
- ASMLEUV gatekeeper
- ASE, AmkorOSAT, not leading edge
- SMICcontrols-constrained
SoIC versus Foveros: the same bet, two houses#
TSMC's SoIC and Intel's Foveros are both 3D die-stacking, and both exist because 2.5D ran out of room. The company that runs the stack sets the ceiling on how much compute you can physically bond together. Today that company is, overwhelmingly, one company.
Key point
None of this is priced like a permanent monopoly. Samsung's SF2 (2nm) is in production and Intel is pushing 18A and 14A. Neither is vaporware. The moat is deep, not permanent.
Four decades of custom compute#
Click a column to unfold the record
Moat migration: transistor, then interposer, then the assembly line itself
The export colander#
Painted as a wall or a sieve, the US-China chip controls are really a colander with deliberately sized holes. The thresholds catch leading-edge logic and the tools that make it, then the line gets re-cut as designers ship parts that sit just under it: A800, then H800, then H20, then H200. The real chokepoint is not any single chip. It is ASML's EUV, which China cannot buy.
Why the recurring bill decides which products survive
Training is a one-time headline. Inference is the tax on every user, every request, and every reasoning token.
packaging stacks gate leading-edge AI compute
TSMC founded: the pure-play foundry begins
the tool China cannot buy, and the real chokepoint
What this signals#
For a buyer, the lesson is that lead times are set by the package, not the print. For an investor, margins follow whoever owns the stack and the pricing power on top of it. For a policymaker, a control drawn at the chip is a control the market designs around within a cycle, while a control drawn at the tool actually holds. The moat is real. It just is not where the spec sheet says it is.
What is advanced packaging, and why does it gate GPU supply?
Advanced packaging bonds multiple dies, high-bandwidth memory, and an interposer into one module. For a modern AI accelerator this assembly, not the transistor, is the scarce step. A design can pass tape-out and still not ship because the CoWoS-class packaging line is full, which is why packaging capacity now sets GPU lead times.
Why can't Samsung or Intel simply take TSMC's packaging business?
Because switching a leading-edge design is qualification-locked: requalifying a chip on a new process and packaging flow costs time and yield. Samsung's SF2 and Intel's 18A are real and improving, but the incumbent's depth in CoWoS and SoIC, plus the cost of moving, keeps the moat deep for now.
What is the difference between AI training cost and inference cost?
Training is a one-time capital cost to build a model. Inference is the recurring cost to run it, and it scales with every user, request, and reasoning token. Training is a headline number; inference is the bill that decides whether a product survives at scale.
What do the US-China chip export controls actually restrict?
They restrict leading-edge logic above set performance and interconnect thresholds, and the tools that make it, most importantly EUV lithography. They deliberately leave older nodes alone. Designers respond by shipping parts that sit just under the line, so the threshold gets re-cut, which is why the controls behave like a colander rather than a wall.
Sources
- US Bureau of Industry and Security: export administration regulationsbis.doc.gov
- NVIDIA data center platforms (Blackwell)nvidia.com
- Intel Foundry: 18A and Foveros advanced packagingintel.com
- Samsung Foundry: SF2 processsemiconductor.samsung.com
- ASML: DUV and EUV lithographyasml.com
- TSMC: advanced packaging (CoWoS, SoIC)tsmc.com
- US Federal Register: BIS advanced computing and semiconductor export controls (interim final rule, Oct 13 2022)federalregister.gov
- US Federal Register: BIS advanced computing export controls update (interim final rule, Oct 25 2023)federalregister.gov
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