CoWoS, SoIC, and Foveros: How Advanced Chip Packaging Actually Works

2.5D versus 3D: what the geometry means#

The split between 2.5D and 3D integration is architectural, and the trade-offs run through every part of a chip's design. In 2.5D, the dies are placed next to each other on an intermediary layer. TSMC's CoWoS, short for Chip on Wafer on Substrate, mounts them on a silicon interposer: a large passive die on a mature node, carrying dense copper wiring and vertical connections that link the active chiplets above it. That silicon wiring reaches pitches far finer than any circuit-board substrate, fine enough to run the thousands-of-wires-wide buses that let high-bandwidth memory sit millimeters from compute. Intel's EMIB takes a lighter route, embedding a small silicon bridge in the package only at the die-to-die seam rather than spanning the whole footprint, which cuts cost and warpage risk.

In 3D, the dies are stacked directly on top of one another. TSMC's SoIC and Intel's Foveros bond them vertically, and the newest versions use hybrid bonding: copper pad joined straight to copper pad and dielectric to dielectric, with no solder micro-bumps in between. Removing the bumps lets the connections shrink below 10 microns in pitch and strips out the electrical parasitics that bumps add. The wires between stacked dies are microns long instead of the millimeters a side-by-side layout needs, which is why 3D reaches interconnect densities no interposer can match. The price is heat, which the comparison below makes concrete.

The CoWoS variants, and why they matter#

CoWoS is not a single recipe, and the variants decide what a package can hold. The differences come down to what the interposer is made of, and that sets the ceiling on how large the package can grow.

That last variant is why the current generation of giant accelerators exists. Nvidia's A100 and H100 were built on CoWoS-S and drove the first packaging crunch, since the GPU die alone sits near the reticle limit and the interposer has to host the HBM stacks on top of it. Blackwell moved to CoWoS-L, because a dual-die GPU with eight HBM stacks needs a package several times a single reticle field, and a silicon interposer stitched that large runs into punishing yield and warpage penalties. Embedding bridges in a larger organic interposer scales far more economically than pushing a stitched silicon slab further.

SoIC and Foveros: the 3D approaches#

TSMC's SoIC, short for System on Integrated Chips, comes in a bumped version (SoIC-P) and a bumpless one (SoIC-X) that uses hybrid bonding at sub-10-micron pitch for high-performance work. AMD is TSMC's lead SoIC customer and the clearest proof that hybrid bonding is a volume technology, not a lab demo: its 3D V-Cache desktop CPUs stack a cache die directly on the compute die, and its Instinct MI300 and MI350 accelerators stack compute and I/O chiplets with SoIC on top of a CoWoS interposer, a 2.5D-plus-3D combination AMD calls 3.5D.

Intel's Foveros started with micro-bumps and vertical connections, using a bottom die as an active interposer that carries power and I/O while the top die holds compute, and it shipped in volume across Intel's Core Ultra laptop chips through the Meteor Lake, Lunar Lake, and Panther Lake generations. Foveros Direct moves to hybrid bonding at sub-10-micron pitch, competitive with SoIC, and Panther Lake bonds its compute tile to a base tile this way on Intel's 18A node. Because Intel co-designs Foveros with its own process nodes and power delivery, it gains real vertical-integration advantages for its own products, but that tight coupling gives external foundry customers a steeper qualification path than TSMC's more neutral model.

Yield is the quiet constraint in every 3D stack. Stacking known-good dies sounds simple, but the post-bond test window is narrow, a hybrid-bonded stack cannot be reworked, and the assembled yield is the product of each die's screened yield and the bond yield itself. Every stack that fails after bonding scraps good dies along with it. At advanced nodes, where logic yields are already under pressure, that multiplication is unforgiving, which is why both TSMC and Intel pour investment into pre-bond die screening and wafer-level test.

Why packaging became the production ceiling#

CoWoS turned into the physical limit on AI accelerators not because the technology failed, but because demand scaled faster than any foundry could responsibly add capacity. A CoWoS package needs an interposer that is itself a large-area die, often bigger than the logic chiplets it hosts, and it follows the same defect-density math as any wafer: larger interposers mean fewer good units per wafer and less volume from a constrained line. On top of that, the specialized bonders and die-placement tools are not interchangeable with ordinary assembly equipment, and their lead times run beyond a year from order to a qualified, running recipe.

So the generational shift makes the ceiling concrete. When several of the largest silicon buyers on earth all pull from one interposer-and-bonding pool, packaging allocation, not logic-wafer availability, sets the shipment limit. Through the peak of accelerator demand, that showed up as allocation queues stretching a year or more for leading customers. The point is blunt for a fabless designer.

The thermal and power wall#

The cost of packing dies this close is physical, and it appears in the silicon before any heatsink. In a 2.5D package, the power-delivery network has to push current through the interposer's wiring and the bump array under each die. At the hundreds of amperes a high-end accelerator draws, the resistance in those paths is not negligible, and the voltage drop has to be covered by margining the supply higher, which costs efficiency.

In a 3D stack the problem sharpens. The bottom die absorbs the heat of the die above it on top of its own dissipation, and the vertical connections carry only so much of it away, so stacking imposes a power-density ceiling on the buried die lower than it could sustain on its own. Architects answer by placing the hottest logic on top, or by accepting a lower voltage or frequency that gives back some of the bandwidth the stacking was meant to win. This is why backside power delivery, which feeds current from beneath the transistors, is arriving in lockstep: it ships on Intel's 18A node and on TSMC's A16 generation, specifically to relieve the power problem that dense integration creates. It is a prerequisite for close integration, not an optional extra.

Where the OSATs fit, and where they stop#

ASE and Amkor, the large outsourced assembly and test houses, are not absent here. They serve a real and profitable market in fan-out and bridge-based packaging for designs that do not need the interconnect density or the thermal management of a full CoWoS or SoIC build. But the ceiling is real. They generally do not own the silicon-interposer line, the hybrid-bonding line, and the co-located leading-edge logic fab that make TSMC's stack cohere, nor the years of joint qualification behind it. A hyperscaler specifying a frontier training accelerator is not weighing CoWoS against an outsourced fan-out option; the bandwidth requirements alone rule it out for that class of chip. The outsourced houses stay competitive where interconnect density is moderate and volumes do not justify the leading packaging lines, which is a large market, just not the frontier-accelerator one.

None of this is quick to copy. A CoWoS- or SoIC-class line is billions of dollars of capital, the specialized bonders come from a short list of vendors with lead times beyond a year, and the process recipes encode thousands of interactions, from interposer warpage to bond reliability under high current, learned only through years of production. That accumulated lead, more than any single patent, is why the competitive stakes in leading-edge silicon now sit in the package as much as in the transistor. The standardization effort around die-to-die interfaces, UCIe, helps chiplets from different vendors interoperate, but it defines the interface, not the packaging: a UCIe-compliant chiplet still needs a CoWoS or SoIC slot to physically build it, and that slot is the scarce thing.