CoWoS, SoIC, and Foveros: How Advanced Chip Packaging Actually Works

How 2.5D and 3D chip packaging differ#

The split between 2.5D and 3D integration is architectural. In 2.5D, the dies sit next to each other on an intermediary layer. TSMC's CoWoS, short for Chip on Wafer on Substrate, mounts them on an interposer: in the original CoWoS-S version, a large piece of silicon placed beneath the logic chips and the HBM stacks, carrying dense copper wiring between them. That silicon wiring is fine enough to run the very wide buses that let high-bandwidth memory sit millimeters from compute. Intel's EMIB takes a lighter route, embedding a small silicon bridge in the package only at the die-to-die seam rather than under the whole footprint. Intel says EMIB has been in mass production since 2017, with Intel and external silicon, for logic-to-logic and logic-to-HBM links. Either way, the package is what puts a processor split into chiplets back together.

In 3D, the dies are stacked on top of one another. The newest versions use hybrid bonding, which IEEE Spectrum described as linking the copper pads on each chip "directly without solder". Removing the solder bumps lets the connections shrink. AMD used a 9-micrometer pitch for the vertical links in its 3D V-Cache CPUs and its MI300 accelerators, IEEE Spectrum reported, and TrendForce reported that TSMC began mass production of SoIC at a 6-micron pitch in 2025. Taiwan's Commercial Times, as relayed by TrendForce in May 2026, reported that SoIC offers 56 times the interconnect density of 2015-era CoWoS. The wires between stacked dies are microns long instead of the millimeters a side-by-side layout needs. The price is heat and bond yield, both covered below.

CoWoS-S vs CoWoS-R vs CoWoS-L#

CoWoS is not a single recipe, and the variants decide what a package can hold. The difference is what the interposer is made of, as SemiWiki's September 2026 comparison of the three lays out, and that sets how large the package can grow.

That last variant is where NVIDIA moved. NVIDIA CEO Jensen Huang said in January 2025, as Reuters reported, that Hopper uses CoWoS-S and that "as we move into Blackwell, we will use largely CoWoS-L", with CoWoS-S capacity moving over to CoWoS-L. TechInsights' analysis of the HGX B200 describes two GPU dies on a TSMC 4nm-class process co-packaged with eight HBM stacks, under the heading "first commercial instance of CoWoS-L". NVIDIA describes Blackwell as two reticle-limited dies joined by a 10 TB/s chip-to-chip link. The packages keep growing: TSMC said it was mass-producing a 5.5-reticle-size CoWoS in 2026 with yields above 98%, and Wei said on the October 2026 earnings call that TSMC is "working on the 9x reticle size and moving into the 14x reticle size".

How SoIC and Foveros stack dies#

TSMC's SoIC, short for System on Integrated Chips, is its 3D stacking technology, and AMD was its first customer, TrendForce reported in 2024, citing MoneyDJ. In the Instinct MI300, AMD stacked GPU chiplets on top of I/O dies with SoIC hybrid bonding, above a CoWoS silicon interposer, as TechInsights describes it; The Register called the result a mix of 2.5D and 3.5D packaging. The MI350 series kept the layered design. AMD's chief Instinct architect, Alan Smith, told Chips and Cheese that the I/O dies sit in an intermediate layer with "the compute that's above those", built up through a CoWoS stack, and AMD's documentation lists, for the MI350X and MI355X, eight compute dies on TSMC N3P, two I/O dies on N6 and eight 12-high HBM3E stacks, 288GB in all. AMD's 3D V-Cache CPUs use hybrid bonding too, stacking a cache chiplet on the processor die at the same 9-micrometer pitch, IEEE Spectrum reported.

Intel's Foveros is a family, and Intel's own packaging page now splits it by geometry. Foveros-S, which Intel says has been in mass production since 2019 with an active base die, is labelled 2.5D. Panther Lake uses it: TechInsights found the Core Ultra X7 358H's compute, graphics and platform controller tiles mounted face-down on a passive silicon base tile, with the compute tile on Intel 18A. Foveros Direct is the 3D version, a "Cu-to-Cu hybrid bonding interface" in Intel's words. TrendForce reported that it reached volume production in the first half of 2026 in the Xeon 6+ (Clearwater Forest) at a 9-micron bond pitch, with 12 compute tiles on Intel 18A on top of three active base tiles on Intel 3. Intel also combines the two methods: its Data Center GPU Max uses what Intel calls EMIB 3.5D, EMIB and Foveros in one package. On TSMC's October 2026 earnings call, Wei granted that a competitor "offers a very competitive solution", while saying CoWoS "is still the number one choice for our customers".

Yield is the quiet constraint in every 3D stack. As Semiconductor Engineering put it in July 2026, pre-bond test can establish that a die works, but post-bond electrical test "remains the most direct evidence that the interface works", and known-good-die selection "doesn't guarantee a successful final interface". Once two good dies are bonded, a bad bond spends both, so the assembled yield is roughly the product of each die's yield and the bond yield. The finer the pitch, the less it takes to spoil a bond: Amkor's Mike Kelly told the publication that "the go-to minimum pitch now is about six microns", and that a single tiny particle is enough.

Why CoWoS capacity limits AI chip supply#

CoWoS became the limit on AI accelerators not because the technology failed but because demand grew faster than the lines. A CoWoS package needs an interposer that is itself a large piece of silicon or RDL, often bigger than the logic dies it hosts, so the bigger the package, the fewer fit on each interposer wafer. TSMC has been adding capacity fast. Huang said in January 2025 that advanced packaging capacity was "probably four times" what it had been less than two years earlier. In August 2026, TSMC vice president Jun He said at the OCP APAC Summit that TSMC had nearly doubled CoWoS capacity each year for three years, TrendForce reported, and Economic Daily News reported that TSMC runs 10 advanced packaging facilities. He added: "We haven't fully met demand yet, but we're getting very close."

The supply chain around CoWoS is tight too. Jun He warned of memory shortages and tight ABF substrate supply. On October 8, 2026, GlobalFoundries announced an agreement with an initial five-year term, which it valued at 2 billion dollars, to supply silicon interposers for TSMC's CoWoS ecosystem from its fab in Malta, New York; volume production has not begun. Asked about the deal on TSMC's October 15 earnings call, Wei said: "we have a little bit of shortage on the back end." When NVIDIA, AMD and others all draw on one interposer-and-bonding pool, packaging allocation, not only logic-wafer supply, sets how many accelerators ship, on top of what TSMC charges for the wafers themselves. The point is blunt for a fabless designer.

Heat and power delivery in stacked chips#

Packing dies this close concentrates power and heat. AMD's Alan Smith told Chips and Cheese that for the MI350, AMD considers the whole stack, from the CoWoS layer through the I/O dies to "the compute that's above those", and looks at "the total thermal density of that whole stack" and the thermal interface materials needed for heat removal. AMD's specification pages rate the MI350X at 1000W and the MI355X at 1400W typical board power.

Backside power delivery, which feeds current from beneath the transistors, is the other lever. Intel's 18A has it as PowerVia, and TechInsights counts Panther Lake's compute tile as Intel's first high-volume client implementation of it. TSMC's first node with backside power, which it calls Super Power Rail, is A16, Semiconductor Engineering reported. Wei said in October 2026 that using backside power "is based on your need for your product", and that some products, like mobile phones, do not use it.

Where ASE, Amkor and GlobalFoundries fit#

ASE and Amkor, the large outsourced assembly and test houses (OSATs), are not absent from advanced packaging. ASE's VIPack platform includes bridge-based fan-out and TSV-based 2.5D and 3D packaging. But the accelerators this page covers, NVIDIA's Blackwell and AMD's MI300 and MI350, are built on TSMC's CoWoS, with SoIC in AMD's case, and TSMC now works with outside companies to extend that supply chain rather than hand it over: it agreed to buy packaging and test services from Amkor and has contracted GlobalFoundries for interposers. ESM China reported, as TrendForce relayed in June 2026, that TSMC plans its own first Arizona advanced packaging plant, with CoWoS and 3D-IC capacity.

None of this is quick to copy. On TSMC's October 2026 call, Wei said TSMC was in "real-world production of 5x reticle size" and added: "I don't believe that anybody can do that today except Taiwan Semiconductor." We have argued that the foundry moat moved to the package. The standard for die-to-die links, UCIe, helps chiplets from different vendors talk to each other. Its latest version, UCIe 3.0, covers the die-to-die physical layer, protocols and software stack, and the consortium says UCIe 2.0 added support for 3D packaging. But it defines the interface, not the package: a UCIe-compliant chiplet still needs a CoWoS, SoIC, EMIB or Foveros line to physically build it.