What Chiplets Are and Why Chipmakers Moved to Them

For most of the industry's history, a processor was one piece of silicon, a single die cut from a wafer. The trend now, especially in high-end CPUs and AI accelerators, is to build a processor out of several smaller dies, called chiplets, wired together inside one package. This is not a marketing gimmick. It is a response to hard economic and physical limits, and it is already how much of the flagship silicon you can buy is made. AMD builds its Ryzen and EPYC CPUs this way; NVIDIA's Blackwell data-center GPU is two dies stitched into one; Apple's Ultra chips fuse two Max dies; Intel splits its recent laptop chips into tiles. Understanding why means starting with a problem as old as chipmaking: defects.

The yield problem#

Chips are made on circular silicon wafers, and the manufacturing process is never perfect. Defects, a speck of contamination or a flaw in one of the layers, land more or less randomly across the wafer. Any die unlucky enough to contain a fatal defect is scrap.

The key insight is how defects interact with die size. A large die is a bigger target, so it is statistically more likely to catch a defect, and when it does, you throw away a large, expensive piece of silicon. Smaller dies each catch fewer defects, and when one is bad, you lose only a small piece. Crucially, the relationship is not linear: as a die grows, the odds that it contains at least one killer defect climb faster than its area, so yield falls off a cliff for the very largest dies. For the same defect rate, cutting a design into several small dies leaves you with far more good silicon per wafer than one big die.

There is a second, quieter yield win. Because each chiplet is tested on its own before assembly, only known-good dies get built into a package. A single stray defect no longer condemns an entire large, expensive processor. It condemns one small die that never makes it into the package. Smaller dies mean better yield, and better yield means lower cost, dramatically lower for the biggest designs.

The trade in one view#

The reticle limit#

There is also a hard ceiling on how big a single die can be. Lithography prints a chip through a mask, and the scanner can only expose a limited area in one shot, known as the reticle limit. Today that field is about 858 square millimeters, 26 by 33 millimeters. You cannot simply keep growing a monolithic die past that boundary. Beyond it, a design has to be split and stitched.

And at the leading edge, that ceiling is set to get lower, not higher. High-NA EUV machines, the newest generation of lithography tools, use anamorphic optics that print over a field roughly half the size, around 429 square millimeters. High-NA is no longer just a lab tool: in mid-2026 Intel became the first to run it in high-volume production, on selected layers of its 18A node. Adoption is still early and selective, but the direction is clear. The tools that print the finest features print them over a smaller area, which pushes splitting a big design into chiplets from optional toward unavoidable on the most advanced nodes.

Chiplets sidestep the ceiling. If you need more total compute than one reticle-sized die can hold, you build several dies and connect them. NVIDIA's Blackwell data-center GPU is the clearest example: two reticle-limited dies joined by a 10 terabyte-per-second die-to-die link and presented to software as a single GPU of 208 billion transistors, far more than any one die could ever hold.

Mixing process nodes#

A quieter advantage is that not every part of a chip benefits equally from the newest, most expensive manufacturing node.

With chiplets, a designer can put the compute cores on a leading node and the input and output functions on a cheaper, well-understood node, then connect them. AMD's server and desktop CPUs are the textbook case: the compute dies, which AMD calls CCDs, ride the newest node while a central I/O die is built on an older, cheaper process. You spend expensive silicon only where it pays off. A monolithic design forces everything onto the same node whether it needs it or not.

What it costs you#

Chiplets are not free wins. The biggest cost is communication between dies. On a single die, signals travel short distances over on-chip wiring. Once you split into chiplets, those signals must cross from one die to another, which costs more power per bit and adds latency compared with staying on a single piece of silicon. Closing that gap is the entire job of advanced packaging: very high-density die-to-die connections, sometimes a silicon bridge or a full interposer to carry dense wiring between dies (Intel's EMIB and TSMC's CoWoS are the well-known versions), and sometimes stacking dies vertically. AMD's 3D V-Cache, an extra cache die stacked directly on top of a compute die, is a shipping example of that vertical approach. An industry standard, UCIe, is now emerging so the die-to-die link does not have to be reinvented for every product.

There is also added design and packaging complexity. You now have multiple dies to design, test, and assemble correctly, and the package itself becomes a sophisticated, active component rather than a passive holder. Get the interconnect wrong and the seams show up as lost performance or wasted power.

Why this became mainstream#

The shift went mainstream because the older path stopped paying off. For decades, each new node made transistors cheaper as well as faster, so building one big die on the latest process was the obvious move. That deal weakened: on recent nodes the cost per transistor has roughly stopped falling, and large dies on the newest processes became punishingly expensive to yield. At the same time, packaging technology matured to the point where die-to-die connections were fast and dense enough to ship in real products.

Those two trends met around the end of the 2010s. AMD's move to chiplets in 2019, with its Zen 2 CPUs, was the mainstream inflection point, and the approach has since spread to GPUs, AI accelerators, and even mainstream laptop chips. Monolithic scaling got more expensive and more limited, and the tools to connect chiplets got good enough, so the economics tipped toward building big products out of small, well-yielding pieces.

A chiplet design is a bet that you can split a processor into pieces and stitch them back together without losing too much to the seams. For large, expensive chips, that bet now usually pays, because the alternative, one enormous monolithic die, is both harder to manufacture and, once you pass the reticle limit, impossible. As packaging keeps improving and the leading-edge reticle set to shrink, expect more products, not fewer, to be built this way.