What Chiplets Are and Why Chipmakers Moved to Them

For most of the industry's history, a processor was one piece of silicon, a single die cut from a wafer. Many high-end processors are now built from several smaller dies, called chiplets, wired together inside one package. AMD has built its EPYC server CPUs this way since the first generation, which joined four identical dies, and its Ryzen 9000X3D desktop CPUs are built around compute dies called CCDs. NVIDIA's Blackwell data-center GPU is two dies that work as one GPU. Apple's M5 Ultra, introduced in August 2026, joins two dual-die M5 Max chips into four dies. Intel's Panther Lake laptop processors are built from tiles: in the Core Ultra X7 358H, TechInsights found compute, graphics and platform-controller tiles mounted on a base tile. Understanding why starts with what a chiplet is, and with a problem as old as chipmaking: defects.

Chiplet vs die#

Every chiplet is a die, but not every die is a chiplet. A die is simply a piece of silicon cut from a finished wafer, and a monolithic processor is one die that holds the whole design. A chiplet is a die built from the start to be one part of a larger chip. The Chiplet Design Exchange, a working group under the Open Compute Project, defines it as "a die specifically designed and optimized for operation within a package in conjunction with other chiplets". It adds that a chiplet typically cannot be packaged separately and still operate effectively, because a conventional die has I/O drivers strong enough to signal over longer electrical distances (as quoted by 3D InCites). IEEE's Electronics Packaging Society puts it the same way: a chiplet is not a package type but part of a packaging architecture, a circuit block "specifically designed to communicate with other chiplets, to form larger more complex ICs." In practice, "chiplet vs die" usually means chiplets versus one big monolithic die, which is the trade the rest of this article explains.

Why smaller dies yield better#

Chips are made on circular silicon wafers, and the manufacturing process is never perfect. Defects, a speck of contamination or a flaw in one of the layers, land more or less randomly across the wafer. Any die unlucky enough to contain a fatal defect is scrap.

Die size is what turns random defects into a cost problem. A large die is a bigger target, and in the simplest model, the Poisson yield model in MIT's manufacturing course notes, the share of good dies falls exponentially with die area. In that model, doubling a die's area squares its yield: a die that comes out good 80 percent of the time becomes one that comes out good 64 percent of the time at twice the size. Real defect densities vary from wafer to wafer, so the same notes also give a refined model, Murphy's, but the measured result, which they headline as an exponential dependence of yield on chip area, points the same way. Cutting a design into several small dies keeps each one in the high-yield range.

Chiplets add a second win: each one is tested before assembly. AMD's chiplet design team described it in a paper summarized by The Next Platform: the chiplets "undergo KGD testing" (known good die), and "for the same fault distribution as in the monolithic case, each potential defect results in discarding only approximately one-fourth of the amount of silicon." For its first EPYC, the team modelled a single 32-core die at 777 square millimeters on a 14nm process, against four chiplets of 213 square millimeters each, 852 in total. Using historical defect density data, AMD estimated that the four-chiplet design cost about 0.59 of the monolithic one, despite using about 10 percent more silicon.

Monolithic die vs chiplets at a glance#

What the reticle limit is#

There is also a hard ceiling on how big a single die can be. A lithography scanner prints a chip's pattern through a mask one exposure field at a time, and ASML lists a maximum scanned exposure field of 26 by 33 millimeters for its NXE:3400B EUV scanner. That is about 858 square millimeters, the figure The Next Platform gives as the barrier for current 300 mm equipment: "No chip can be etched bigger than that." AMD's chiplet team called the reticle limit "a practical ceiling on how large silicon die can be manufactured." Past it, a design has to be split into several dies or printed in separate exposures that are stitched together.

On the newest scanners the field is smaller. ASML's High-NA EUV systems, the EXE line, raise the numerical aperture from 0.33 to 0.55 and use anamorphic optics, which ASML says give exposure fields half the size of its NXE scanners: 26 by 16.5 millimeters, Bits&Chips reported, or about 429 square millimeters. Larger dies on those tools have to be stitched from two exposures. High-NA is in production use: in July 2026, ASML reported that Intel Foundry had entered high-volume manufacturing of a subset of its Core Ultra Series 3 (Panther Lake) processors using High-NA EUV on specific Intel 18A layers, which ASML called the first high-volume logic product made with it. In September 2026, ASML and TSMC announced an initiative to move the industry from 6-inch to 12-inch photomasks, which they said would remove stitching constraints; for now, the companies said, High-NA is being adopted for production with the current 6-inch masks. How EUV lithography works covers the machines themselves.

Chiplets sidestep the ceiling. If a product needs more silicon than one field can print, it can be built from several dies connected in the package. NVIDIA says every Blackwell product has two reticle-limited dies joined by a 10 terabyte-per-second chip-to-chip interconnect, working as a unified single GPU with 208 billion transistors. Apple's M5 Ultra goes further: Apple says its UltraFusion interconnect connects two dual-die M5 Max chips into four dies with more than 4.4 terabytes per second of inter-die bandwidth, which behave as a single unified processor. How those dies are packaged, side by side on an interposer or stacked, is its own subject, and so is the high-bandwidth memory that sits beside AI chips in the package.

Why chiplets can mix process nodes#

Not every part of a chip benefits equally from the newest, most expensive manufacturing node. IEEE's Electronics Packaging Society names the cost of leading-edge nodes, the lack of scaling in significant design blocks such as analog, and die sizes reaching the reticle limit as the forces driving chips to be split up.

With chiplets, a designer can put each block on the node that suits it and connect them in the package. AMD did this in 2019 with its second-generation EPYC, code-named Rome: The Register described eight compute chiplets made on TSMC's 7nm process around a central I/O die made on 14nm, nine dies in one package. AMD's Instinct MI350X and MI355X accelerators keep the same split, with eight vertically stacked compute dies on N3P and two I/O dies on N6. Leading-edge silicon is spent only where it pays off; a monolithic design puts every block on one node.

The downsides of chiplets#

Chiplets are not free wins. The biggest cost is communication between dies: The Next Platform, summarizing AMD's paper, lists longer routes with potentially higher impedances, lower available bandwidth, and higher power consumption and/or higher latency. Advanced packaging exists to shrink that gap. Intel's EMIB embeds a small silicon bridge in the package substrate where two dies meet, and Intel says it has been in mass production since 2017. TSMC's CoWoS-S puts the dies on one large silicon interposer, and CoWoS-L uses a redistribution-layer interposer with small silicon bridges, as SemiWiki explains. AMD's 3D V-Cache goes vertical, stacking an SRAM cache die and a compute die with hybrid bonds; in the second generation, Chips and Cheese found, AMD moved the SRAM die beneath the compute die. UCIe, an open industry standard for the die-to-die link, aims to let chiplets from different vendors work together: its latest version, UCIe 3.0, supports 48 and 64 GT/s data rates; the top rate doubles the 32 GT/s of UCIe 2.0.

There is also more design work. AMD's team wrote that "a chiplet design requires more engineering work upfront to partition the SoC into the right number and kinds of chiplets," and testing and debugging have to be repeated across far more pieces. Get the split or the interconnect wrong and the seams show up as lost performance or wasted power.

Why chipmakers moved to chiplets#

The older path stopped paying off. For decades, each new node made transistors cheaper as well as faster, so one big die on the latest process was the obvious move. That deal weakened. AMD's team wrote that the cost to make a chip "has been steadily climbing, with a sharp increase in the latest generations," driven by extra mask layers for multiple patterning and harder manufacturing, and that chipmakers were waiting longer for each new node and paying more for it. Google's Milind Shah said the cost of 100 million transistor gates was about the same as in the 28nm generation, with 5nm and 3nm chips slightly pricier per transistor, PC Gamer reported in 2024. TSMC's pricing power covers what leading-edge wafers cost. Packaging matured at the same time: Intel's EMIB bridge has been in mass production since 2017.

AMD's server line shows the shift. Its first-generation EPYC was built from four identical chiplets, and the second generation, which AMD launched in August 2019, split compute and I/O onto different nodes. The approach has since spread to GPUs and AI accelerators (NVIDIA's Blackwell, AMD's Instinct MI350), to laptop processors (Intel's Panther Lake) and to Apple's desktop chips (M5 Ultra).

A chiplet design is a bet that a processor can be split into pieces and stitched back together without losing too much at the seams. For AMD's first EPYC, its own modelling says the bet paid, at about 0.59 of the monolithic cost. Our reading is that the pressure keeps growing: one huge die yields worse, it cannot be printed in one exposure past the reticle limit, and on High-NA scanners the field is half the size.