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ArticlehardwareDeep read

The US–China Chip Export Controls: Where They Restrict, and Where They Don't

Ahmad JAug 11, 20265 minUpdated Sep 15, 2026

Painted as a wall or a sieve, the US-China chip controls are really a colander with deliberately sized holes. This maps what the thresholds actually catch, where enforcement leaks, and why the line keeps moving, from FinFET nodes and TPP limits to the A800-to-H200 design-around loop.

A deep read: the full picture, with the receipts.

Key takeaways

US chip controls target specific technical thresholds such as FinFET architecture, a TPP of around 4,800 for AI accelerators, DRAM at 18nm half-pitch or below, and NAND at 128 layers or more, leaving trailing-edge nodes largely unrestricted.
NVIDIA's design-around cycle shows how BIS rules and chip products chase each other: the A800 and H800 complied with the 2022 rule until BIS removed the interconnect parameter in October 2023, and the subsequent H20 was blocked in April 2025, leading to a charge of around 4.5 billion dollars on stranded inventory.
EUV lithography has never been exported to China, while the contested band of advanced DUV immersion tools is now governed by a patchwork of Dutch, EU, Japanese, and US rules that do not fully align, creating enforcement seams.
China's SMIC can produce 7nm-class logic using DUV multi-patterning without EUV, but the approach carries higher costs and lower yields, and domestic AI accelerator production faces a bottleneck in high-bandwidth memory supply.

Signalstrong6independent sources

The United States' export controls on China's access to advanced chips are usually described one of two ways: an impenetrable wall, or a leaky sieve. Neither is right. The controls behave more like a colander: a surface engineered with holes of a very specific size. Some things are caught by design; others pass through by design; and a third category slips through seams the designers didn't intend. Telling those apart, and understanding why each exists, is the difference between reading the semiconductor trade accurately and repeating headlines.

What Actually Gets Controlled: The Thresholds#

US controls don't restrict "chips." They restrict capability, measured against technical thresholds written into the Export Administration Regulations (EAR) and administered by the Commerce Department's Bureau of Industry and Security (BIS). Three families of metrics do most of the work:

The metric family	Where the line is drawn
Logic process node and transistor architecture	Not a marketing nanometer but the physics of the transistor. Chips built on a non-planar architecture (FinFET or gate-all-around), roughly the 16nm/14nm generation and everything denser, fall inside the controlled zone, as does the fabrication equipment capable of producing sub-16nm logic. This is why the real fight is over tools, not just finished chips
AI accelerator performance	For GPUs and AI accelerators, BIS uses Total Processing Performance (TPP), a function of raw math throughput and numerical precision, paired with Performance Density, TPP divided by the die area actually doing the work. The original October 2022 rule set the bar with a compute-performance threshold, recast in a 2023 revision as a TPP of around 4,800, and a chip-to-chip interconnect ceiling of 600 GB/s. By early 2026 the ceiling for a chip even eligible for licensed export to China sat around an H200-class part: very roughly, a TPP in the several thousands and total memory bandwidth in the multiple-thousands of GB/s
Memory	Controlled by density, not speed of thought: DRAM at an 18nm half-pitch or below, NAND flash at 128 layers or more. In December 2024 BIS added high-bandwidth memory (HBM), the stacked DRAM that feeds AI accelerators, on the logic that a restricted GPU is far less useful if it can't be fed data fast enough

The exact figures move. The mechanism doesn't.

These are surgical, not sweeping.

That precision is the whole design philosophy: a "small yard, high fence" around the leading edge.

What the Controls Deliberately Leave Alone#

Below those lines sits most of the semiconductor industry, and it is largely untouched, on purpose:

What is left alone	What that means
Trailing-edge nodes	Chips on mature nodes, 28nm and up: the microcontrollers, power-management ICs, display drivers and automotive parts that make up the bulk of the world's silicon by volume. Not restricted. China can make them and buy them freely
Mature manufacturing equipment	Tools that top out below the advanced-node line are generally exportable, so Chinese fabs can keep buying equipment to expand trailing-edge capacity. This is exactly why the policy debate has since shifted toward China's flood of mature-node output
Below-the-line design software	EDA restrictions bite hardest at the leading edge, notably gate-all-around design tools. Software for designing mature-node chips mostly isn't captured

The dividing line is capability, not ubiquity. What's controlled is defined by how advanced a thing is, not how common or commercially important it is.

Where Enforcement Actually Leaks#

Even inside the controlled zone, a rule on paper isn't a rule in a warehouse. The recurring gaps:

Where it leaks	How the leak works
Third-country transshipment	Hardware routed through a permissive intermediary, a distributor in a third country, before reaching the real end user. The paperwork names one destination; the pallet goes to another
Shell buyers and hidden end users	Front companies and freshly created entities place orders the controls, built around named, listed entities, weren't watching for. BIS chases this with the Entity List, but new shells appear faster than they are added
The gray zone of "good enough" hardware	When the top-tier part is blocked, demand flows to whatever is legally the next rung down. Less evasion than the controls' own edge effect, and it drives the design-around cycle below

These aren't hypotheticals; they're documented patterns. Each is a seam where the neat geometry of the thresholds meets the messy geometry of global logistics.

The Design-Around Cycle: A800, H800, H20, H200#

The clearest illustration of how thresholds and business collide is NVIDIA's China lineup.

Move	What happened
A100 and H100	Exceeded both the compute and the 600 GB/s interconnect limits, so they were blocked
A800 and H800	NVIDIA cut the interconnect below the line and shipped them: legal by the letter of the 2022 rule
October 2023	BIS deleted the interconnect parameter precisely to close that gap, which swept in the A800, H800, the L40S and even the gaming-class RTX 4090
H20	NVIDIA engineered it to sit under the redrawn line
April 2025	A licence requirement imposed on the H20 anyway; NVIDIA booked a multibillion-dollar charge on stranded inventory
8 December 2025 → 13 January 2026	A presidential announcement, then a BIS rule making the more capable H200 and comparable parts case-by-case rather than refused outright

In April 2025 the government imposed a license requirement on the H20 anyway, and NVIDIA booked a multibillion-dollar charge (around $4.5 billion, against an initial estimate of up to $5.5 billion) on stranded inventory. Then the pendulum swung back. Following a presidential announcement on 8 December 2025, BIS issued a rule on 13 January 2026 revising its licensing policy so that applications to export the more capable H200, along with AMD's MI325X and comparable parts, are reviewed case by case rather than refused outright.

The conditions are worth reading as policy design rather than as a green light:

The condition	What the applicant must show
Production capacity	The sale will not reduce global semiconductor production capacity currently available to US customers
Buyer compliance	The Chinese purchaser must have adopted export compliance procedures, including customer screening
Independent testing	The product must have passed independent third-party testing in the United States to verify its performance and security

ASML: DUV vs. EUV#

No company sits closer to the fulcrum than ASML, the sole maker of extreme-ultraviolet (EUV) lithography, the tooling required for the most advanced nodes. The interesting story is one step down, in deep-ultraviolet (DUV) immersion tools.

The tool	Where it stands
EUV	Never exported to China. That is the hard wall
DUV immersion	For years the loophole: advanced enough to let Chinese fabs reach 7nm through multi-patterning, but only loosely controlled. That gap has closed considerably. The Netherlands introduced national licensing for its most advanced immersion systems, the TWINSCAN NXT:2000i and successors, and in November 2025 the EU folded those controls into the bloc-wide export list; US lawmakers have pushed to choke off DUV immersion entirely

The tool

Where it stands

EUV

Never exported to China. That is the hard wall

DUV immersion

For years the loophole: advanced enough to let Chinese fabs reach 7nm through multi-patterning, but only loosely controlled. That gap has closed considerably. The Netherlands introduced national licensing for its most advanced immersion systems, the TWINSCAN NXT:2000i and successors, and in November 2025 the EU folded those controls into the bloc-wide export list; US lawmakers have pushed to choke off DUV immersion entirely

China's Domestic Answer: Substitute or Stopgap?#

China's drive for self-sufficiency has produced real progress and real ceilings, at the same time:

The champion	The progress, and the ceiling
SMIC	China's largest foundry manufactures 7nm-class logic, the N+2 node behind Huawei's Kirin 9000S and 9020, using DUV multi-patterning, and has pushed toward a 5nm-class (N+3) process, all without EUV. A genuine achievement, but multi-patterning without EUV means more process steps, lower yields and higher cost per good die. The binding constraint is economics and volume, not only the physics
Huawei	The Kirin line, in the Mate 60/70/80 phones, proves domestic logic can ship at scale. The Ascend 910C AI accelerator is competitive on inference, but its ceiling is set less by the compute die than by supply: dwindling stockpiles of foreign-made dies push production onto SMIC wafers, and the real bottleneck is high-bandwidth memory
CXMT and YMTC	China's DRAM/HBM and NAND champions are expanding, but run into both the equipment controls above them and the yield-and-cost reality of catching the leading edge

Domestic fabrication is filling the trailing- and middle-tier holes. It is not yet a full substitute for the leading edge, which is exactly what the controls are aimed at.

Allied Coordination: Synchronized or Full of Seams?#

The controls only work as a coalition. The US writes rules with extraterritorial reach (the Foreign Direct Product Rule), but the physical choke points live in the Netherlands (ASML) and Japan (Tokyo Electron, key materials). Where the allies align (EUV, the most advanced DUV) the fence holds. Where they lag or diverge (timing, DUV scope, which Chinese entities get named) seams open, and supply chains route through them.

Coordination is the load-bearing wall of the entire structure, and it's renegotiated country by country.

Reading the Financials#

You don't have to trust the policy language; the income statements tell the same story.

The company	What the filings show
NVIDIA	The multibillion-dollar H20 write-down, and its effectively-foreclosed China disclosure. The sharp end
Lam Research (LRCX) and Applied Materials (AMAT)	Both have flagged material China-related revenue impacts on the tools side
ASML	Has guided China down to roughly a fifth of sales, from about a third the year before

The controls show up where they can't be spun: in the numbers.

The Takeaway#

The US-China chip controls aren't a wall and they aren't a sieve. They're a colander with deliberately sized holes: a small yard of leading-edge logic, top-tier AI accelerators, HBM, and EUV/advanced-DUV tooling fenced high, and everything below that line, most of the industry by volume, left to flow. The real story lives in three places at once: the precise thresholds, the seams where enforcement meets logistics, and the policy lever that keeps moving the line. Read all three, and the trade makes sense. Read only the headline, and it won't.