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Table of contents7 sections · tap to jump
  1. Tokens Come From Moving Weights, Not Computing Them
  2. The Math Behind the Limit
  3. Why Different Hardware Behaves So Differently
  4. Quantisation: Shrinking the Problem to Fit Your Pipe
  5. KV Cache: A Second Memory Problem
  6. Practical Implications for Hardware Selection
  7. The Software Stack Sets How Close You Get to the Ceiling
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Memory Bandwidth, Not Compute, Limits Local LLM Speed

Ahmad JAug 11, 20265 minUpdated Sep 14, 2026

Why TFLOPS don't matter for inference: token generation is memory-bound, and the bottleneck is how fast weights reach your chip.

A deep read: the full picture, with the receipts.

Signalstrong2independent sources

Memory bandwidth is the dominant factor in local LLM inference speed, not your GPU's TFLOP rating or your CPU's clock frequency. Understanding why requires looking at how transformers actually consume hardware resources.

Tokens Come From Moving Weights, Not Computing Them#

When a large language model generates a single token, it loads most of its weights from memory, runs a relatively small number of multiply-accumulate operations on them, and discards those weights until the next token. That pattern is the core problem.

Generating tokens is fundamentally memory-bound, not compute-bound. The relevant metric is arithmetic intensity: floating-point operations per byte of memory traffic. Training with large batches achieves high arithmetic intensity: weights are reused across many examples. Autoregressive inference at batch size one has extremely low arithmetic intensity: you load each weight, use it once or twice, and move on.

The theoretical peak TFLOPS printed on a product sheet become nearly irrelevant for single-user local inference.

The bottleneck is memory bandwidth: how fast weights travel from storage into compute units.

The Math Behind the Limit#

Think through the logic:

The modelSize at 4-bitMemory traffic per token
7 billion parametersRoughly 3.5 GBEssentially that whole set of active weights, read from memory once
70 billion parametersAround 35 GBThe same read, ten times larger, for every single token

Divide model size by your device's memory bandwidth and you get a rough floor on per-token latency: the minimum time even with perfect utilisation. Doubling bandwidth roughly doubles token generation speed.

This is why a modest GPU with very high memory bandwidth consistently outperforms a compute-monster chip with slower memory at batch size one. The teraflops sit idle, waiting for data the memory bus cannot deliver fast enough.

Why Different Hardware Behaves So Differently#

Hardware classIts memory story
Discrete consumer GPUsGDDR memory at moderate bandwidth, with VRAM capacities that may not fit larger models. When a model exceeds VRAM, inference spills to system RAM over PCIe, a bus orders of magnitude narrower than VRAM bandwidth, and token generation slows dramatically
High-end discrete GPUsHBM (High Bandwidth Memory), a stacked architecture with dramatically higher bandwidth than GDDR, plus tens or hundreds of gigabytes of VRAM. They dominate server inference not primarily because they compute faster, but because they move weights faster
Apple Silicon (M-series)Unified memory: the CPU, GPU and Neural Engine share one physical pool over a very wide internal bus. Bandwidth is substantially higher than typical discrete-GPU GDDR, and with no PCIe bottleneck surprisingly large quantised models run at respectable token rates. The trade-off is capacity, capped by what is soldered to the board
Dedicated AI acceleratorsBuilt to maximise memory bandwidth per watt for transformer inference, often sacrificing the general-purpose flexibility GPUs provide

Quantisation: Shrinking the Problem to Fit Your Pipe#

Quantisation trades model quality for inference speed through a pure memory bandwidth mechanism.

Lower precision means fewer bytes per parameter. Fewer bytes means less memory traffic per token. On fixed bandwidth, less traffic means higher throughput:

PrecisionBytes per parameter, against FP16What you get
FP16 (16-bit)The baselineFull fidelity, maximum bytes, slowest on given hardware
Q8 (8-bit)HalfTypically around twice the token rate, with small quality loss
Q4 (4-bit)A quarterCan double the token rate again, with noticeable quality degradation depending on the method
Q2–Q3Less againExtremely compact, but quality often degrades enough to matter

Methods like GGUF k-quants, GPTQ, and AWQ preserve the most important weight information while compressing aggressively. But speed gains flow through the same mechanism: reduced memory traffic. Quantisation helps most when you're deepest in the memory-bound regime, which is almost always true at local inference batch sizes.

KV Cache: A Second Memory Problem#

The key-value (KV) cache creates a second memory pressure that grows with context length. During inference, the model stores intermediate attention keys and values for every prior token. This cache lives in fast memory and is read on every forward pass.

As context growsThe bandwidth consequence
The KV cache grows linearly with context lengthFor long contexts it can dwarf the model weights themselves
Weights and cache are both read on every forward passLoading weights, and loading and storing the KV cache, compete for the same bus at the same moment
Higher-bandwidth hardware degrades more gracefullyWhich is partly why KV cache quantisation and sliding-window attention exist

Longer-context inference is slower not just because there is more computation, but because there is more memory traffic.

Practical Implications for Hardware Selection#

The ruleWhy it holds
Prioritise bandwidth over computeWhen comparing two GPUs, read memory bandwidth alongside VRAM capacity. Higher bandwidth at the same VRAM often serves inference better
VRAM capacity sets the ceilingA model forced onto slower system RAM stalls regardless of fast-memory bandwidth. Capacity and bandwidth together define what is feasible
Unified memory eliminates one bottleneckA large, fast, unified pool avoids the PCIe spill problem: a genuine architectural advantage for local inference, not marketing
Batch size changes the calculusA local API server handling multiple concurrent requests runs at higher batch sizes, which raises arithmetic intensity and brings compute back into play. The memory-bound logic is strongest for interactive single-user generation
System RAM and CPU bandwidth matter for CPU inferenceRunning entirely on CPU, llama.cpp without a capable GPU, makes CPU memory bandwidth and RAM speed the direct bottleneck. DDR5 systems with high-frequency memory have a meaningful edge over older DDR4 machines

The Software Stack Sets How Close You Get to the Ceiling#

Hardware bandwidth is the ceiling; software determines how close you get. Inference runtimes like llama.cpp, MLX, and ONNX Runtime use different strategies (memory layout optimisations, custom kernels, asynchronous transfers) to saturate available bandwidth more efficiently. The same hardware can deliver meaningfully different token rates depending on how well the runtime exploits it.

Tiling strategies, fused kernels, and prefetching exist to hide memory latency and maximise bandwidth utilisation. Choosing a well-optimised runtime matters, particularly on novel hardware where generic code paths may leave significant bandwidth untapped.


When evaluating any local-AI hardware claim, the first question to ask is not "how many TFLOPS?" but "how wide is the memory pipe, and can the model fit inside it?"

Sources

  1. Dao et al., FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness (arXiv)arxiv.org
  2. Kwon et al., Efficient Memory Management for LLM Serving with PagedAttention / vLLM (arXiv)arxiv.org
  3. llama.cpp, LLM inference in C/C++ (project repository)github.com

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